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smsc PAC1720 smsc confidential datasheet revision 1.1 (12-08-11) datasheet product features PAC1720 dual high-side current sense monitor with power calculation general description the PAC1720 is a dual high-side bi-directional current sensing monitor with prec ision voltage measurement capabilities. each sensor measures the voltage developed across an external sense resistor to represent the high-side current of a battery or voltage regulator. the PAC1720 also measures the sense+ pin voltage and calculates average power over the integration period. the PAC1720 can be programmed to assert the alert pin when high and low limits are exceeded for current sense and bus voltage. available in a rohs compliant 3 x 3mm 10-pin dfn package. the PAC1720 device is good for measuring dynamic power. the long integration time allows for extending system polling cycles without losing any power consumption information. in addition the alert ensures that transient events are captured between the polling cycles. applications ? notebook and desktop computers ? industrial ? power management systems ? embedded applications features ? dual high-side current sensor ? current measurement is integrated over 2.5ms to 2.6sec with up to 11-bit resolution ? 1% current measurement accuracy in positive range ? measures v source voltages ? calculates proportional power ? v source voltage range 0v to 40v ? bi-directional current sensing ? auto-zero input offset voltage ? digital averaging ? adjustable sampling time and resolution ? 5a typical standby current ? programmable sense voltage range ? 10mv, 20mv, 40mv, and 80mv ? power supply range 3.0v to 5.5v ? wide temperature operatin g range: -40c to +85c ? alert output for voltage and current out of limit transients between sampling interval ? smbus 2.0 communications interface ? address selectable by resistor decode ? sample time configurable from 2.5ms-320ms ? with averaging effective sampling times up to 2.6sec ? 3x3 mm dfn-10 package block diagram smbus interface smclk smdata addr_sel sense2+ sense2- voltage registers configuration current registers current limits voltage limits alert power register current measurement voltage measurement power management vdd gnd configuration current measurement voltage measurement sense1+ sense1- analog mux
reel size is 4,000 pieces this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs ordering number package features PAC1720-1-aia-tr 10-pin 3 x 3 dfn (lead free rohs compliant) smbus 2.0 communications interface, alert pin, dual sensor dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 2 smsc PAC1720 smsc confidential datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000 or 1 (800) 443-semi copyright ? 2011 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. ordering information:
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 3 revision 1.1 (12-08-11) smsc confidential datasheet table of contents chapter 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chapter 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 chapter 3 communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 system management smbus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 smbus start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.2 smbus address and rd / wr bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.3 smbus ack and nack bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.4 smbus stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.5 smbus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.6 smbus and i 2 c compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 smbus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 write byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 read byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.3 send byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.4 receive byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.5 alert response address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 3.3 i 2 c protocols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 chapter 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 conversion cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.1 conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 current measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 voltage measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 power calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 alert output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 data read interlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 conversion rate register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 one-shot register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 high limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7 low limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.8 vsource sampling configur ation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.9 vsense sampling configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 5.9.1 ch1 vsense sampling configuration - 0bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.9.2 ch2 vsense sampling configuration - 0ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.10 sense voltage registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.11 vsource voltage registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.12 power ratio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.13 v sense limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.14 vsource voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 4 smsc PAC1720 smsc confidential datasheet 5.15 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.16 smsc id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.17 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 6 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 PAC1720 package drawing (10-pin dfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 PAC1720 package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 chapter 7 application usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 electrical overstress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 PAC1720 internal filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 do not apply a filter across the curren t shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4 initial device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 chapter 8 typical operating curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 chapter 9 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 5 revision 1.1 (12-08-11) smsc confidential datasheet list of figures figure 1.1 PAC1720 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3.1 smbus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4.1 PAC1720 system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6.1 10-pin dfn package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6.2 10-pin dfn package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6.3 10-pin dfn recommended pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6.4 PAC1720 package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 7.1 equivalent internal esd circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 7.2 PAC1720 with unnecessary filters on the input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 8.1 idd vs vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8.2 idd vs vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8.3 idd vs vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8.4 isense+ pin current vs vbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8.5 isense+ pin bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8.6 isense- pin bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8.7 isense+ pin leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 8.8 isense- pin leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 8.9 isense+ pin current vs vbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 6 smsc PAC1720 smsc confidential datasheet list of tables table 1.1 pin description for PAC1720 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1.2 pin types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2.2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2.3 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.1 addr_sel resistor setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.2 protocol format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3.3 write byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3.4 read byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3.5 send byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.6 receive byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.7 alert response address protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.8 block write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3.9 block read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5.1 register set in hexadecimal order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5.3 conversion rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.4 conversion rate for measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.5 one-shot register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.6 channel mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.7 high limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.8 low limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.9 voltage sampling configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.10 voltage source sampling time settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.11 voltage source averaging settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.12 vsense sampling configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.13 current sensing averaging settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.14 current sensing sampling time sett ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.15 current sensing range settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.16 sense voltage registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.17 v sense data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.18 v sense data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.19 vsource voltage registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.20 power ratio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.21 v sense limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.22 vsource voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.23 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.24 manufacturer id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.25 revision register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9.1 PAC1720 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 7 revision 1.1 (12-08-11) smsc confidential datasheet chapter 1 pin description the pin types are described in ta b l e 1 . 2 . all pins labeled with (5v) are 5v tolerant. all pins labeled with (40v) are 40v tolerant. figure 1.1 PAC1720 pin diagram table 1.1 pin description for PAC1720 pin number pin name pin function pin type 1 sense1+ positive current sense measurement point ai (40v) 2 sense1- negative current sense measurement point ai (40v) 3 sense2+ positive current sense measurement point ai (40v) 4 sense2- negative current sense measurement point ai (40v) 5 gnd ground power 6 addr_sel selects smbus address ai (5v) 7alert active low output - requires pull - up resistor od (5v) 8 smdata smbus data input/output - requires pull-up resistor diod (5v) 9 smclk smbus clock input - requires external pull-up resistor di (5v) 10 vdd positive power supply voltage power (5v) gnd smclk vdd 1 2 3 4 5 smdata sense1+ sense1- sense2+ gnd sense2- alert addr_sel PAC1720 3mm x 3mm dfn 10 9 8 7 6
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 8 smsc PAC1720 smsc confidential datasheet table 1.2 pin types pin type description power this pin is used to supply power or ground to the device. ai analog input - this pin is used as an input for analog signals. od open drain digital output - this pin is used as a digital output. it is open drain and requires a pull-up resistor. this pin is 5v tolerant. di digital input - this pin is used for digital inputs. this pin is 5v tolerant. diod open drain digital input / output - this pin is bi-directional. it is open drain and requires a pull-up resistor. this pin is 5v tolerant.
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 9 revision 1.1 (12-08-11) smsc confidential datasheet chapter 2 electrical characteristics note 2.1 stresses at or above those values listed could cause permanent damage to the device. this is a stress rating only, and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. prolonged stresses above the stated operating levels and below the absolute maximum ratings may degrade device performance and lead to permanent damage. note 2.2 all voltages are relative to ground. note 2.3 the package power dissipation specification assumes a thermal via design with the thermal landing be soldered to the pcb ground plane with four 0.3048mm (12 mil) vias (where applicable). note 2.4 junction to ambient ( ja ) is dependent on the design of the thermal vias. table 2.1 absolute maximum ratings supply voltage, gnd to vdd -0.3 to 6.0 v analog input voltage, gnd to sense pins -0.3 to 42.0 v differential input voltage, se nse- to sense+ -42.0 to 42.0 v voltage on 5v tolerant pins with respect to gnd gnd-0.3 to vdd+0.3 v input current to any pin except vdd or gnd + 10 ma output short circuit (to gnd or vdd) continuous package power dissipation 10-pin dfn (up to t a = 85c) 0.5 w junction to ambient ( ja ) (dfn-10 package) 78 c/w operating ambient temperature range -40 to 85 c storage temperature range -55 to 150 c esd rating - smclk, smdata, and alert pins - hbm 8000 v esd rating - all other pins - hbm 2000 v
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 10 smsc PAC1720 smsc confidential datasheet 2.1 electrical specifications table 2.2 electrical specifications max values are at t a = -40c to 85, v dd = 3v to 5.5v, v source = 0v to 40v typ values are at t a = 25c, v dd = 3.3v, v source = 24v, v sense = (sense+ - sense-) = 0v current sense full scale range = 80mv unless otherwise noted. characteristic symbol min typ max unit conditions / notes dc power voltage on sense+ v source 040v v dd range v dd 3.0 5.5 v vdd pin supply current i dd 0.525 1.3 ma both measurement channels enabled. continuous conversions (see table 5.4 ) 13 50 a both measurement channels enabled. 1 conversion / second (see table 5.4 ) vsrc_samp_time = 2.5ms cs_samp_time = 2.5ms no smbus communications vdd pin supply current i dd 360 900 a one measurement channel enabled. continuous conversions (see table 5.4 ) 10 35 a one measurement channel enabled. 1 conversion / second (see table 5.4 ) vsrc_samp_time = 2.5ms cs_samp_time = 2.5ms no smbus communications v dd rise rate v dd_rise 0.03 v/ms 0 to 3v in 100ms v dd standby current i dd_stby 5.5 15 a standby state sensex+ pin bias current i sense + 100 150 a -80mv < v sense < 80mv active state sensex- pin bias current i sense- 0.1 1 a -80mv < v sense < 80mv active state sensex+ pin leakage current i sense+ _leak 0.01 1 a v sense = 0v standby state sensex- pin leakage current i sense- _leak 0.01 1 a v sense = 0v standby state current sense sense+ / sense- pins common mode voltage range v cm 0 40 v common mode voltage on sense pins, referenced to ground v sense differential input voltage range v diff -80 +80 mv voltage between sense+ and sense- pins
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 11 revision 1.1 (12-08-11) smsc confidential datasheet current sense power supply rejection ratio psrr_cs 10 v/v 3.0v < vdd < 5.5v full scale range () (see section 5.9 ) fsr -10 10 mv 1 lsb = 4.885v 11-bit data resolution -20 20 mv 1 lsb = 9.77v 11-bit data resolution -40 40 mv 1 lsb = 19.54v 11-bit data resolution -80 80 mv 1 lsb = 39.08v 11-bit data resolution common mode rejection v sense _cmrr 80 100 db common mode rejection, 0v < v source < 40v current sense offset error voltage offset error voltage (referred to input) v os 15 v fsr = + 10mv 15 v fsr = + 20mv 20 v fsr = + 40mv 40 v fsr = + 80mv current sense total measurement error to ta l e r r o r (positive range) (see section 4.3 ) v sense _tot_err 0.5 1 % fsr fsr = 0 to +10mv 0.3 0.6 % fsr fsr = 0 to +20mv 0.2 0.4 % fsr fsr = 0 to +40mv 0.2 0.4 % fsr fsr = 0 to +80mv to ta l e r r o r (negative range) (see section 4.3 ) v sense _tot_err -1 -1.3 -1.6 % fsr fsr = -10mv to 0 -1 -1.3 -1.6 % fsr fsr = -20mv to 0 -1 -1.3 -1.6 % fsr fsr = -40mv to 0 -1.6 -2 -2.4 % fsr fsr = -80mv to 0 v source voltage measurement power supply rejection ratio psrr 10 mv/v 3.0v < v dd < 5.5v v source error () v source_ err 0.15 0.3 % fsv power ratio total power ratio measurement error () (positive range) p ratio _err 1 % fsr fsr = 0 to +10mv, 0 to +20mv, 0 to +40mv, or 0 to +80mv table 2.2 electrical specifications (continued) max values are at t a = -40c to 85, v dd = 3v to 5.5v, v source = 0v to 40v typ values are at t a = 25c, v dd = 3.3v, v source = 24v, v sense = (sense+ - sense-) = 0v current sense full scale range = 80mv unless otherwise noted. characteristic symbol min typ max unit conditions / notes
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 12 smsc PAC1720 smsc confidential datasheet 2.2 smbus electri cal specifications total power ratio measurement error () (negative range) p ratio _err 2 % fsr fsr = -10mv to 0, -20mv to 0, -40mv to 0, or -80mv to 0 first power ratio ready t conv_p 220 ms time after power up before p ratio updated digital i/o pins (smclk, smdata, alert ) pull-up voltage range v pullup 3.0 5.5 v pull-up voltage for smbus and alert pins time to first communications t comm 25 ms input high voltage v ih 2.0 v smclk, smdata od pins pulled up to v pullup input low voltage v il 0.8 v output low voltage v ol 0.4 v od pin pulled to v pullup 3ma current sink leakage current () i leak 5 a powered or unpowered ta < 85c table 2.3 smbus elect rical specifications max values are at t a = -40c to 85, v dd = 3v to 5.5v, v source = 0v to 40v typ values are at t a = 25c, v dd = 3.3v, v pullup = 3.3v, v source = 24v, v sense = (sense+ - sense-) = 0v current sense full scale range = 80mv unless otherwise noted. characteristic symbol min typ max units conditions input capacitance c in 410 pf clock frequency f smb 10 400 khz spike suppression t sp 100 ns bus free time stop to start t buf 1.3 s start setup time t su:sta 0.6 s start hold time t hd:sta 0.6 s stop setup time t su:sto 0.6 s data hold time t hd:dat 0 s when transmitting to the master data hold time t hd:dat 0.3 s when receiving from the master table 2.2 electrical specifications (continued) max values are at t a = -40c to 85, v dd = 3v to 5.5v, v source = 0v to 40v typ values are at t a = 25c, v dd = 3.3v, v source = 24v, v sense = (sense+ - sense-) = 0v current sense full scale range = 80mv unless otherwise noted. characteristic symbol min typ max unit conditions / notes
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 13 revision 1.1 (12-08-11) smsc confidential datasheet data setup time t su:dat 0.6 s clock low period t low 1.3 s clock high period t high 0.6 s clock / data fall time t fall 300 ns min = 20+0.1c load ns clock / data rise time t rise 300 ns min = 20+0.1c load ns capacitive load c load 400 pf total per bus line table 2.3 smbus electrical specifications (continued) max values are at t a = -40c to 85, v dd = 3v to 5.5v, v source = 0v to 40v typ values are at t a = 25c, v dd = 3.3v, v pullup = 3.3v, v source = 24v, v sense = (sense+ - sense-) = 0v current sense full scale range = 80mv unless otherwise noted. characteristic symbol min typ max units conditions
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 14 smsc PAC1720 smsc confidential datasheet chapter 3 communications 3.1 system management smbus interface protocol the PAC1720 communicates with a host controller th rough the smbus. the smbus is a two-wire serial communication protocol between a co mputer host and its peripheral devices. a detailed timing diagram is shown in figure 3.1 . stretching of the smclk signal is supported; however, the PAC1720 will not stretch the clock signal. 3.1.1 smbus start bit the smbus start bit is defined as a transition of th e smbus data line from a logic ?1? state to a logic ?0? state while the smbus clock line is in a logic ?1? state. 3.1.2 smbus address and rd / wr bit the smbus address byte consists of the 7-bit client address followed by a 1-bit rd / wr indicator. if this rd / wr bit is a logic ?0?, the smbus host is writi ng data to the client device. if this rd / wr bit is a logic ?1?, the smbus host is re ading data from the client device. the PAC1720 smbus address is determined by a si ngle resistor connected between ground and the addr_sel pin as shown in table 3.1 . figure 3.1 smbus timing diagram smdata smclk t buf p s s - start condition p - stop condition p s t high t low t hd:sta t su:sto t hd:sta t hd:dat t su:dat t su:sta t fall t rise
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 15 revision 1.1 (12-08-11) smsc confidential datasheet all smbus data bytes are sent most significant bit first and composed of 8-bits of information. 3.1.3 smbus ack and nack bits the smbus client will acknowledge all data bytes that it receives (as well as the client address if it matches and the ara address if the alert pin is asserted). this is done by the client device pulling the smbus data line low after the 8th bit of each byte that is transmitted. the host will nack (not acknowledge) the data re ceived from the client by holding the smbus data line high after the 8th data bit has been sent. 3.1.4 smbus stop bit the smbus stop bit is defined as a transition of the smbus data line from a logic ?0? state to a logic ?1? state while the smbus clock line is in a logi c ?1? state. when the PAC1720 detects an smbus stop bit, and it has been communicating with the smbus pr otocol, it will reset its client interface and prepare to receive further communications. 3.1.5 smbus timeout the PAC1720 includes an smbus timeout feature. following a 30ms period of inactivity on the smbus, the device will timeout and reset the smbus interface. the timeout functionality defaults to disabled and can be enabled by writing to the timeout bit (see section 5.2, "configuration register" ). 3.1.6 smbus and i 2 c compliance the major differences between smbus and i 2 c devices are highlighted here. for more information, refer to the smbus 2.0 and i 2 c specifications. 1. PAC1720 supports i 2 c fast mode at 400khz. this covers the smbus max time of 100khz. 2. minimum frequency for smbus communications is 10khz. 3. the smbus client protocol will reset if the clo ck is held at a logic ?0? for longer than 30ms. this timeout functionality is disabled by default in the PAC1720 and can be enabled by writing to the timeout bit. i 2 c does not have a timeout. table 3.1 addr_sel resistor setting resistor (5%) smbus address resistor (5%) smbus address 0 1001_100(r/w) 1600 0101_000(r/w) 100 1001_101(r/w) 2000 0101_001(r/w) 180 1001_110(r/w) 2700 0101_010(r/w) 300 1001_111(r/w) 3600 0101_011(r/w) 430 1001_000(r/w) 5600 0101_100(r/w) 560 1001_001(r/w) 9100 0101_101(r/w) 750 1001_010(r/w) 20000 0101_110(r/w) 1270 1001_011(r/w) open 0011_000(r/w)
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 16 smsc PAC1720 smsc confidential datasheet 4. the smbus client protocol will reset if both the clock and data lines are held at a logic ?1? for longer than 200us (idle condition). this function is disabled by default in the PAC1720 and can be enabled by setting the timeout bit. i 2 c does not have an idle condition. 5. i 2 c devices do not support the alert response addre ss functionality (which is optional for smbus). 6. i 2 c devices support block read and block write differently. i 2 c protocol allows for unlimited number of bytes to be sent in either direction. the smbus protocol require s that an additional data byte indicating number of bytes to read / write is transmitted. the PAC1720 supports i 2 c formatting only. 3.2 smbus protocols the PAC1720 is smbus 2.0 compatible and supports write byte, read byte, send byte, and receive byte as valid protocols. it will respond to the al ert response address protocol but is not in full compliance. all of the protocols listed below use the convention in ta b l e 3 . 2 . 3.2.1 write byte the write byte is used to write one byte of data to the registers, as shown in table 3.3 : 3.2.2 read byte the read byte protocol is used to read one byte of data from the registers, as shown in ta b l e 3 . 4 . 3.2.3 send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol, as shown in table 3.5 . application note: the send byte protocol is not functional in the standby state. table 3.2 protocol format data sent to device data sent to the host # of bits sent # of bits sent table 3.3 write byte protocol start slave address wr ack register address ack register data ack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 xxh 0 0 -> 1 table 3.4 read byte protocol start slave address wr ack register address ack start slave address rd ack register data nack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 0 -> 1 yyyy_yyy 1 0 xxh 1 0 -> 1
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 17 revision 1.1 (12-08-11) smsc confidential datasheet 3.2.4 receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via send byte). application note: the receive byte protocol is not functional in the standby state. 3.2.5 alert response address the alert output can be used as a processor interr upt or as an smbus alert when configured to operate as an interrupt. when it detects that the alert pin is asserted, the host will send the alert response address (ara) to the general address of 0001_100xb. all devices with active interrupts will respond with their client address, as shown in ta b l e 3 . 7 . the PAC1720 will respond to the ara in the following way if the alert pin is asserted. 1. send slave address and verify that full slav e address was sent (i.e. the smbus communication from the device was not prematurely stopped due to a bus contention event). 2. set the mask bit to clear the alert pin. 3.3 i 2 c protocols the PAC1720 supports i 2 c block read and block write. the protocols listed below use the convention in ta b l e 3 . 2 . 3.3.1 block write the block write is used to write multiple data byte s to a group of contiguous registers, as shown in table 3.8 . table 3.5 send byte protocol start slave address wr ack register address ack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 0 -> 1 table 3.6 receive byte protocol start slave address rd ack register data nack stop 1 -> 0 yyyy_yyy 1 0 xxh 1 0 -> 1 table 3.7 alert response address protocol start alert response address rd ack device address nack stop 1 -> 0 0001_100 1 0 yyyy_yyy 1 0 -> 1
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 18 smsc PAC1720 smsc confidential datasheet 3.3.2 block read the block read is used to read multiple data bytes from a group of contiguous registers, as shown in table 3.9 . table 3.8 block write protocol start slave address wr ack register address ack register data ack 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 register data ack register data ack register data ack stop xxh 0 xxh 0 xxh 0 0 -> 1 table 3.9 block read protocol start slave address wr ack register address ack start slave address rd ack register data 1->0 yyyy_yyy 0 0 xxh 0 1 ->0 yyyy_yyy 1 0 xxh ack register data ack register data ack register data ack register data nack stop 0 xxh 0 xxh 0 xxh 0 xxh 1 0 -> 1
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 19 revision 1.1 (12-08-11) smsc confidential datasheet chapter 4 general description the PAC1720 is a bi-directional dual high-side current sensing device with precision voltage measurement capabilities. it measures the volt age developed across an external sense resistor to represent the high-side current of a battery or voltage regulator. the PAC1720 also measures the sense1+ and sense2+ pin voltages (v sourcex ) and calculates average power over the integration period. the PAC1720 measures the differential voltage across an external sense resistor, digitizes it with a variable resolution (6-bit to 11-bit plus sign) sigma-delta adc, and transmits via the smbus or i 2 c protocol. the current range allows fo r large variations in measured current with high accuracy and low voltage drop across the resistor. the PAC1720 has programmable high and low limits for current sense and bus voltage with a maskable alert signal to the host when an out-of-limit measurement occurs. a system diagram is shown in figure 4.1 . 4.1 power states the PAC1720 has three states of operation: ? active - the PAC1720 initiates conversion cycles for the programmed conversion rate. ? standby - this is the lowest powe r state. there are no conversion cycles. the majority of circuitry is powered down to reduce supply current to a mi nimum. the smbus is active and the part will return requested data. to enter the standby state, disable all four measurements (see section 5.2, "configuration register" ). ? one-shot - while the device is in standby, the host can initiate a conversion cycle on demand (see section 5.4, "one-shot register" ). after the conversion cycle is co mplete, the device will return to the standby state. figure 4.1 PAC1720 system diagram PAC1720 host mcu smdata smclk alert v source 0v ? 40v sense resistors vdd sense2- sense2+ 3.0v to 5.5v addr_sel gnd 3.0v to 5.5v sense1+ sense1-
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 20 smsc PAC1720 smsc confidential datasheet 4.2 conversion cycle the conversion cycle is the period of time in which the measurements are taken and the data is updated. in the active state, individual measurements can be disabled. in the standby state, all measurements are updated. during the conversion cycle, bot h channels begin taking measuremen ts at the same time. the v sense sample is taken first for its programmed sample time. then the v source sample is taken for its programmed sample time. digital averaging may be applied to average the last 2 to 8 samples. sample time and digital averaging have separate controls for v sense and v source as well as for each channel (see section 5.8, "vsource samp ling configuration register" and section 5.9, "vsense sampling configuration registers" ). at the end of the conversion cycle, the enabled measurements are updated. the power ratio, high limit status (which includes a conv_done status bit), and low limit status registers are always updated. the alert pin will be asserted, by default, if an y out-of-limit conditions exist (see section 4.6, "alert output" ). 4.2.1 conversion rate for power management in the active state, a conv ersion rate can be programmed. conversion rate specifies how often measurement data should be updated. updates once pe r second is the lowest setting (see section 5.3, "conversion rate register" ). if the actual sampling time for both measurements (v source and v sense ) is greater than 1 / conversion rate for either channel, the PAC1720 wi ll override the programmed conversion rate and operate in continuous mode. 4.3 current measurement the PAC1720 includes two high-side current sensing circuits. these circuits measure the voltage, v sense , induced across fixed external current sense resistors, r sense , and store the voltage as a signed 11-bit (by default) number in the sense voltage registers. the PAC1720 current sensing operates in one of f our bipolar full scale ranges (fsr): 10mv, 20mv, 40mv, or 80mv (see section 5.9 ). the default fsr is 80mv. full scale current (fsc) can be calculated from: where: [1] fsc is the full scale current fsr is + 10mv, + 20mv, + 40mv, or + 80mv (see section 5.9 ) r sense is the external sense resistor value fsc fsr r sense --------------------- =
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 21 revision 1.1 (12-08-11) smsc confidential datasheet actual current through r sense can then be calculated using: as an example, suppose the system is drawing 1.65a through a 10m resistor, the fsr is set for + 20mv, and sample time is 80ms. using equation [1] , the fsc is 2a. the measured v sense is 1.65a * 10m = 16.5mv. this value of v sense is represented in the sens e voltage registers as 69_8h (0110_1001_1000b or 1688d) ignoring the 4 lower bits of the low byte as these are always 0. this value, when applied to equation [2] , results in an i bus current of 1.649a. for a negative voltage the sense voltage registers are read as 96_0h (again ignoring the lower 4 bits of the low byte as these are always 0). to calculat e current, the binary value is first converted from two?s complement by inverting the bits and adding one: 96_80h = 1001_0110_1000b. inverting equals 0110_1001_0111b (69_7h) and adding one gives 0110_1001_1000b (69_8h). this results in the same calculated value as in the positive voltage case. 4.4 voltage measurement the pin voltage is measured on the supply side of sense1+ and sense2+ and stored as an unsigned 11-bit number in the vsource voltage registers as v source (see section 5.11 ). full scale voltage (fsv) is given by the maximum value of the vsense voltage registers: actual voltage at sense+ can be calculated using: where: [2] i bus is the actual bus current fsc is the full scale current value (from equation [1] ) v sense is the value read from the sense voltage registers (in decimal), ignoring the four lowest bits which are always zero (see section 5.10 ) denominator is determined by the sample time, as shown in table 5.14, "current sensing sampling time settings" where: [3] fsv is the full scale voltage denominator is determined by the sample time, as shown in table 5.10, "voltage source sampling time settings" . where: [4] v source is the actual voltage on the sensex+ pin fsv is the full scale voltage (from equation [3] ) v source is the value read from the vsource voltage registers (in decimal), ignoring the lowest five bits which are always zero. (see section 5.11, "vsource voltage registers" ) denominator is determined by the sample time, as shown in table 5.10, "voltage source sampling time settings" . i bus fsc v sense denominator ------------------------------------- = fsv 40 40 denominator ------------------------------------- ? = v source _ pin fsv v source denominator ------------------------------------- =
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 22 smsc PAC1720 smsc confidential datasheet as an example using 10-bit resolution, suppose that the actual pin voltage is 24v. the vsource voltage registers will report a value of 99_80h (1001_1001_10xx_xxxxb) in 10-bit resolution (default). when reading the data, the lower 5 bits are always ignored. because the default operation is to measure the vsource voltage with 10-bit resolution, the 6th bi t is likewise ignored. therefore, decoding the upper 10-bits results in a decimal value of 614. this value, when applied in equation [4] , results in v source_pin equal to 23.98v. as an example using 11-bit resolution, suppose that the actual pin voltage is 10.65v. the vsource voltage registers will report a value of 44_10h (0100_0100_001x_xxxxb). because the lower 5-bits are ignored, the decimal result is 545d. this value, when applied in equation [4] , results in v source_pin equal to 10.64v. the v source voltage may also be determined by scaling each bit set by the indicated bit weighting as described in section 5.11 . 4.5 power calculation the PAC1720 may be used to determine the average power provided at the source side of sense1+ and sense2+ using the value, p ratio , contained in the power ratio registers (see section 5.12 ). the value represents the percentage of maximum calculable power. p ratio is mathematically generated by multiplying the absolute values of v sense and v source (see section 4.3 and section 4.4 ) and is stored as a 16-bit number. p ratio is updated whenever either v sense or v source is updated. full scale power can be calculated from: actual power drawn from the source can be calculated using: as an example, suppose that the actual pin voltage is 10.65v, the current through a 10m resistor is 1.65a, the fsr is set for + 20mv, and the sample times are the defaults. the fsc value is 2a per equation [1] . the fsv value is 39.96v per equation [3] . using equation [5] , the fsp value is 79.92w. applying p = v * i, the expected power is 17. 57w which is 21.98% of the fsp value. reading the power ratio registers will report p ratio as 38_47h (0011_1000_0100_0111b or 14,407d). using equation [6] , this value results in a calculated bus power of 17.57w which is ~21.98% of the fsp value. where: [5] fsp is the full scale power fsc is the full scale current (from equation [1] ) fsv is the full scale voltage (from equation [3] ) where: [6] p bus is the actual power provid ed by the source measured at sense+ fsp is the full scale power (from equation [5] ) p ratio is the value read from the power ratio registers (in decimal) (see section 5.12 ) fsp fsc fsv = p bus fsp p ratio 65 535 , ------------------- =
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 23 revision 1.1 (12-08-11) smsc confidential datasheet 4.6 alert output the alert pin is an open drain output and requires a pull-up resistor to v pullup. the alert pin is used as an interrupt signal or as an smbus alert signal that allows an smbus slave to communicate an error condition to the master. one or more smbus alert outputs can be hard-wired together. the alert pin will be asserted (by default) if the measured v source voltage or v sense voltage are out of limit (> high limit or < low limit). the alert pin will remain asserted as long as an out-of-limit condition remains. once the out-of-limit condition has been removed, the alert pin will remain asserted until the appropriate status bits are cleared. the alert pin can be masked for all out-of-limit me asurements by setting the mask_all bit (see section 5.2, "configuration register" ) or for an individual out-of-limit measurement (see section 5.5, "mask register" ). once the alert pin has been masked, it will be de-asserted if no unmasked out- of-limit conditions exist. any interrupt conditions that occur while the alert pin is masked will update the status registers normally. the alert pin can be asserted for 5us when all measurements are finished (if enabled by setting conv_done_en - see section 5.2, "configuration register" ).
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 24 smsc PAC1720 smsc confidential datasheet chapter 5 register descriptions the registers shown in ta b l e 5 . 1 are accessible through the smbus. an entry of ?-? indicates that the bit is not used and will always read ?0?. table 5.1 register set in hexadecimal order register address r/w register name function default value page 00h r/w configuration controls the general operation of the device 00h page 26 01h r/w conversion rate controls the conversion rate for updating measurement data in the active state 03h page 27 02h w one-shot in standby, a write to this register initiates a conversion cycle, updating all measurements 00h page 27 03h r/w channel mask register controls the maski ng of out-of-limit measurements 00h page 28 04h r-c high limit status status bits for the high limits 00h page 29 05h r-c low limit status status bits for the low limits 00h page 29 0ah r/w vsource sampling configuration controls v source voltage sampling settings 88h page 30 0bh r/w ch1 vsense sampling configuration controls v sense sampling settings for channel 1 53h page 31 0ch r/w ch2 vsense sampling configuration controls v sense sampling settings for channel 2 53h page 31 0dh r ch1 sense voltage high byte stores the voltage measured across channel 1 r sense 00h page 32 0eh r ch1 sense voltage low byte 00h page 32 0fh r ch2 sense voltage high byte stores the voltage measured across channel 2 r sense 00h page 32 10h r ch2 sense voltage low byte 00h page 32 11 r ch1 vsource voltage high byte stores voltage measured at channel 1 v source 00h page 34 12 r ch1 vsource voltage low byte 00h page 34 13h r ch2 vsource voltage high byte stores voltage measured at channel 2 v source 00h page 34 14h r ch2 vsource voltage low byte 00h page 34
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 25 revision 1.1 (12-08-11) smsc confidential datasheet 5.1 data read interlock when any measurement high byte register is read (v source or v sense ), the corresponding low byte is copied into an internal ?shadow? register. the user is free to read the low byte at any time and be guaranteed that it will correspond to the previously re ad high byte. regardless if the low byte is read or not, reading from the same hi gh byte register again will automati cally refresh this stored low byte data. 15h r ch1 power ratio high byte stores the power ratio value for channel 1 00h page 35 16h r ch1 power ratio low byte 00h page 35 17h r ch2 power ratio high byte stores the power ratio value for channel 2 00h page 35 18h r ch2 power ratio low byte 00h page 35 19h r/w ch1 sense voltage high limit stores the high limit for channel 1 v sense 7fh page 35 1ah r/w ch2 sense voltage high limit stores the high limit for channel 2 v sense 7fh page 35 1bh r/w ch1 sense voltage low limit stores the low or negative limit for channel 1 v sense voltage 80h page 35 1ch r/w ch2 sense voltage low limit stores the low or negative limit for channel 2 v sense voltage 80h page 35 1dh r/w ch1 vsource voltage high limit stores the high limit for the channel 1 v source voltage ffh page 36 1eh r/w ch2 vsource voltage high limit stores the high limit for the channel 2 v source voltage ffh page 36 1fh r/w ch1 vsource voltage low limit stores the low limit for the channel 1 v source voltage 00h page 36 20h r/w ch2 vsource voltage low limit stores the low limit for the channel 2 v source voltage 00h page 36 fdh r product id stores a fixed value that identifies each product 57h page 36 feh r smsc id stores a fixed value that represents smsc 5dh page 36 ffh r revision stores a fixed value that represents the revision number 81h page 37 table 5.1 register set in hexadecimal order (continued) register address r/w register name function default value page
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 26 smsc PAC1720 smsc confidential datasheet 5.2 configuration register the configuration register controls the basic operation of the device. bit 6 - conv_done_en - enables the alert pin to be asserted when the conversion cycle is finished. ? ?0? (default) - the alert pin will not be asserted when the conversion cycle is finished. ? ?1? - the alert pin will be asse rted for 5us when the conversion cycle is finished. bit 5 - mask_all - masks the alert pin from asserting due to out-of-limit conditions. ? ?0? (default) - the alert pin is not masked. if any of the appropriate status bits are set, the alert pin will be asserted. ? ?1? - the alert pin is masked. it will not be asserted for any interrupt cond ition. the status registers will be updated normally. bit 4 - ch2_ imeas_dis - disables v sense measurement for channel 2. application note: ch2_imeas_dis should only be c hanged from ?1? (disabled) to ?0? (enabled) when the PAC1720 is in the standby state. to do this, disable all measurements in the configuration register 00h, wait fo r the conversion cycle to complete by monitoring t he xmeas_dis bits until they stay set to ?1?, and then enable t he desired measurements with one register write. ? ?0? (default) - the device is measuring sense voltage for current sense channel 2. ? ?1? - the device is not measuring the sense volt age for current sense channel 2. it will update ch2 sense voltage registers when a one-shot command is given. bit 3 - ch2_vmeas_dis - disables v source measurement for channel 2. ? ?0? (default) - the device is measuring v source voltage for current sense channel 2. ? ?1? - the device is not measuring the v source voltage. it will update the ch2 vsource voltage registers when a one-shot command is given. bit 2 - timeout - determines whether the timeout / idle function is enabled. ? ?0? (default) - the timeout / idle feature is disabled. ? ?1? - the timeout / idle feature is enabled. if the smclk line is held low for more than 30ms or both the clock and data lines are held at a logic ?1? for longer than 200us, the device will reset the communications protocol. bit 1 - ch1_imeas_dis - disables the v sense measurement for current sense channel 1. application note: ch1_imeas_dis should only be c hanged from ?1? (disabled) to ?0? (enabled) when the PAC1720 is in the standby state. to do this, disable all measurements in the configuration register 00h, wait fo r the conversion cycle to complete by monitoring t he xmeas_dis bits until they stay set to ?1?, and then enable t he desired measurements with one register write. ? ?0? (default) - the device is measuring se nse voltage for current sense channel 1. ? ?1? - the device is not measuring the sense volt age. it will update ch1 sense voltage registers when a one-shot command is given. table 5.2 configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 00h r/w configuration - conv_ done_ en mask_ all ch2_ imeas_ dis ch2_ vmeas_ dis time out ch1_ imeas_ dis ch1_ vmeas_ dis 00h
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 27 revision 1.1 (12-08-11) smsc confidential datasheet bit 0 - ch1_vmeas_dis - disables v source measurement for current sense channel 1. ? ?0? (default) - the device is measuring v source voltage for current sense channel 1. ? ?1? - the device is not measuring the v source voltage. it will update ch1 vsource voltage registers when a one-shot command is given. 5.3 conversion rate register the conversion rate register controls how often v sense , v source , p ratio , and the status bits are updated in the active state (see section 4.2.1, "conversion rate" ). bits 1 - 0 - conv_rate - determines the conversion rate as shown in table 5.4 . application note: the conversion rate should only be updated when the PAC1720 is in the standby state. to do this, disable the measurements in the confi guration register 00h, wait for the conversion cycle to complete by monitoring the xmeas_dis bi ts in 00h until they stay set to ?1?, change the conversion rate, and then enable the desired measurements. 5.4 one-shot register when the device is in the standby state, writing to the one-shot register will initiate a conversion cycle and update all measurements (see section 4.2, "conversion cycle" ). application note: do not write to the one-shot register when the PAC1720 is in the active state (i.e., when any measurements are enabled in th e configuration register 00h). table 5.3 conversion rate register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 01h r/w conversion rate ------ conv_ rate 03h table 5.4 conversion rate for measurement conv_rate[2:0] conversion rate 10 0 0 1 per sec 0 1 2 per sec 1 0 4 per sec 1 1 continuous (default) table 5.5 one-shot register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 02h w one-shot writing to this register initiates a si ngle conversion cycle. data is not stored in this register, so it always reads 00h. 00h
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 28 smsc PAC1720 smsc confidential datasheet 5.5 mask register the channel mask register controls individual out-of-limit measurement masking. when a measurement is masked, the alert pin will not be asserted when the masked measurement is out of limit. application note: if the mask_all bit in the configuration register 00h is set to mask the alert pin, this register will have no effect. bit - 3 - ch2_vsense_mask - masks the alert pin from asserting when the channel 2 v sense value meets or exceeds the high limit or drops below the low limit. ? ?0? (default) - the channel 2 v sense voltage measurement can cause the alert pin to be asserted (if enabled). ? ?1? - the channel 2 v sense voltage measurement cannot cause the alert pin to be asserted (if enabled). bit - 2 - ch2_vsrc_mask - masks the alert pin from asserting when the channel 2 v source value meets or exceeds the high limit or drops below the low limit. ? ?0? (default) - the channel 2 v source voltage measurement can cause the alert pin to be asserted (if enabled). ? ?1? - the channel 2 v source voltage measurement cannot cause the alert pin to be asserted (if enabled). bit - 1 - ch1_vsense_mask - masks the alert pin from asserting when the channel 1 v sense value meets or exceeds the high limit or drops below the low limit. ? ?0? (default) - the channel 1 v sense voltage measurement can cause the alert pin to be asserted (if enabled). ? ?1? - the channel 1 v sense voltage measurement cannot cause the alert pin to be asserted (if enabled). bit - 0 - ch1_vsrc_mask - masks the alert pin from asserting when the channel 1 v source value meets or exceeds the high limit or drops below the low limit. ? ?0? (default) - the channel 1 v source voltage measurement can cause the alert pin to be asserted (if enabled). ? ?1? - the channel 1 v source voltage measurement cannot cause the alert pin to be asserted (if enabled). table 5.6 channel mask register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 03h r/w channel mask ---- ch2_ vsense_ mask ch2_ vsrc_ mask ch1_ vsense_ mask ch1_ vsrc_ mask 00h
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 29 revision 1.1 (12-08-11) smsc confidential datasheet 5.6 high limit status register the high limit status register contains the status bits that are set when a voltage measurement high limit is met or exceeded. once set, the status bi ts will remain set until read. reading from the high limit status register will clear all bits if the error condition has been removed. bit - 7 - conv_done - indicates that the conversion cycle (see section 4.2, "conversion cycle" ) is complete. this bit is cleared when read. bit - 3 - ch2_vsense_high - this bit is set when the channel 2 v sense value meets or exceeds its programmed high limit. bit - 2 - ch2_vsrc_high - this bit is set when the channel 2 v source value meets or exceeds its programmed high limit. bit - 1 - ch1_vsense_high - this bit is set when the channel 1 v sense value meets or exceeds its programmed high limit. bit - 0 - ch1_vsrc_high - this bit is set when the channel 1 v source value meets or exceeds its programmed high limit. 5.7 low limit status register the low limit status register contains the status bits that are set when a voltage measurement drops below the low limit. once set, the status bits will remain set until read. reading from the low limit status register will clear all bits if the error condition has been removed. bit 3 - ch2_vsense_low - this bit is set when the channel 2 v sense value drops below its programmed low limit. bit 2 - ch2_vsrc_low - this bit is set when the channel 2 v source value drops below its programmed low limit. bit 1 - ch1_vsense_low - this bit is set when the channel 1 v sense value drops below its programmed low limit. bit 0 - ch1_vsrc_low - this bit is set when the channel 1 v source value drops below its programmed low limit. table 5.7 high limit status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 04h r-c high limit status conv_ done - - - ch2_ vsense_ high ch2_ vsrc _ high ch1_ vsense_ high ch1_ vsrc_ high 00h table 5.8 low limit status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 05h r-c low limit status ----ch2_ vsense_ low ch2_ vsrc_ low ch1_ vsense_ low ch1_ vsrc_ low 00h
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 30 smsc PAC1720 smsc confidential datasheet 5.8 vsource sampling configuration register the voltage sampling configuration register controls sampling settings for the v source measurement. bits 7 - 6 - ch2_vsrc_samp_time[1:0] - determines the channel 2 v source measurement sample time, as shown in ta b l e 5 . 1 0 . this will affect the resolution of the data presented in the vsource voltage registers. bits 5 - 4 - ch2_vsrc_avg[1:0] - controls the digital averaging that is applied to the channel 2 v source measurement, as shown in table 5.11 . this determines the numbe r of consecutive samples that are averaged. bits 3 - 2 - ch1_vsrc_samp_time[1:0] - determines the channel 1 v source measurement sample time, as shown in ta b l e 5 . 1 0 . this will affect the resolution of the data presented in the vsource voltage registers. bits 1 - 0 - ch1_vsrc_avg[1:0] - controls the digital averaging that is applied to the channel 1 v source measurement, as shown in table 5.11 . this determines the numbe r of consecutive samples that are averaged. note 5.1 the equation [3] denominator is equal to the equation [4] denominator + 1. table 5.9 voltage sampling configuration register addrr/wregisterb7b6b5b4b3b2b1b0default 0ah r/w vsource sampling config ch2_ vsrc_samp_ time[1:0] ch2_ vsrc_avg[1:0] ch1_ vsrc_samp_ time[1:0] ch1_ vsrc_avg[1:0] 88h table 5.10 voltage source sampling time settings vsrc_samp_time vsource sample time equation [3] denominator (see note 5.1 ) equation [4] denominator (see note 5.1 ) 0 0 2.5ms (data = 8 bits) 256 255 0 1 5ms (data = 9 bits) 512 511 1 0 10ms (data = 10 bits) (default) 1024 1023 1 1 20ms (data = 11 bits) 2048 2047 table 5.11 voltage source averaging settings vsrc_avg samples to average 0 0 disabled (default) 01 2 10 4 11 8
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 31 revision 1.1 (12-08-11) smsc confidential datasheet 5.9 vsense sampling configuration registers the vsense sampling configuration registers control sampling settings for the v sense measurement. 5.9.1 ch1 vsense sampli ng configuration - 0bh bits 6 - 4 - ch1_cs_samp_time[2:0] - determine the channel 1 v sense measurement sample time, as shown in ta b l e 5 . 1 4 . this will affect the resolution of the data in the ch1 sense voltage registers. bits 3 - 2 - ch1_cs_samp_avg[1:0] - controls the di gital averaging that is applied to the channel 1 v sense measurement, as shown in ta b l e 5 . 1 3 . this determines the number of consecutive samples that are averaged. bits 1 - 0 - ch1_cs_rng - determines the current sense full scale range as shown in table 5.15 . 5.9.2 ch2 vsense sampli ng configuration - 0ch bits 6 - 4 - ch2_cs_samp_time[2:0] - determines the channel 2 v sense voltage measurement sample time, as shown in table 5.14 . this will affect the resolution of the data in the ch2 sense voltage registers. bits 3 - 2 - ch2_cs_samp_avg[1:0] - controls the di gital averaging that is applied to the channel 2 v sense measurement, as shown in ta b l e 5 . 1 3 . this determines the number of consecutive samples that are averaged. bits 1 - 0 - ch2_cs_rn - determines t he current sense fsr, as shown in table 5.15 . table 5.12 vsense sampling configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 0bh r/w ch1 vsense sampling config - ch1_ cs_samp_time[2:0] ch1_ cs_samp_ avg[1:0] ch1_ cs_rng 53h 0ch r/w ch2 vsense sampling config - ch2_ cs_samp_time[2:0] ch2_ cs_samp_ avg[1:0] ch2_ cs_rng 53h table 5.13 current sensing averaging settings cs_samp_avg[1:0] samples to average 0 0 disabled (default) 01 2 10 4 11 8
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 32 smsc PAC1720 smsc confidential datasheet note 5.2 160ms sampling time has built-in 2x analog oversampling using adc at 12-bit resolution. note 5.3 320ms sampling time has built-in 4x analog oversampling using adc at 13-bit resolution. 5.10 sense voltage registers table 5.14 current sensing sampling time settings cs_samp_time[2:0] current sensor sample time equation [2] denominator 0 0 0 2.5ms (data = sign + 6 bits) 63 0 0 1 5ms (data = sign + 7 bits) 127 0 1 0 10ms (data = sign + 8 bits) 255 0 1 1 20ms (data = sign + 9 bits) 511 1 0 0 40ms (data = sign + 10 bits) 1023 1 0 1 80ms (data = sign + 11 bits) (default) 2047 1 1 0 160ms (data = sign + 11 bits) (see note 5.2 ) 2047 1 1 1 320ms (data = sign + 11 bits) (see note 5.3 ) 2047 table 5.15 current sensing range settings cs_rng[1:0] full scale range 0 0 -10mv to 10mv 0 1 -20mv to 20mv 1 0 -40mv to 40mv 1 1 -80mv to 80mv (default) table 5.16 sense voltage registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 0dh r ch1 sense voltage high byte sign 1024 512 256 128 64 32 16 00h 0eh r ch1 sense voltage low byte 8421 00h 0fh r ch2 sense voltage high byte sign 1024 512 256 128 64 32 16 00h 10h r ch2 sense voltage low byte 8421 00h
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 33 revision 1.1 (12-08-11) smsc confidential datasheet the sense voltage register s store the measured v sense value (see section 4.3, "current measurement" ). note that the bit weighting values are for representation of the voltage relative to full scale. there is no internal scaling of data and all normal binary bit weightings still apply. the sense voltage registers data format is standard 2?s complement format with the positive full scale value (7f_fh) and negative full scale value (80_0h) equal to the programmed fsr (see section 5.9 ). the sign bit indicates the direction of current flow. if the sign bit is ?0?, current is flowing through r sense from the sense+ pin to the sense- pin. if the si gn bit is ?1?, the current is flowing through r sense from the sense- pin to the sense+ pin. data resolution is dependent upon sampling time as shown in ta b l e 5 . 1 8 . the data format (assuming 11-bit resolution) is shown in table 5.17 . this data will scale directly with the sampling time. table 5.17 v sense data format v sense binary hex (as read by registers) - full scale 1000_0000_0000 80_0h -2 lsb 1111_1111_1110 ff_eh -1 lsb 1111_1111_1111 ff_fh 0 0000_0000_0000 00_0h +1 lsb 0000_0000_0001 00_1h +2 lsb 0000_0000_0010 00_2h +full scale - 1 lsb 0111_1111_1111 7f_fh table 5.18 v sense data resolution sampling time resolution () 10mv 20mv 40mv 80mv 2.5ms 156.3v 312.5v 625.0v 1.250mv 5ms 78.13v 156.3v 312.5v 625.0v 10ms 39.06v 78.13v 156.3v 312.5v 20ms 19.53v 39.06v 78.13v 156.3v 40ms 9.76v 19.53v 39.06v 78.13v > 80ms 4.88v 9.76v 19.53v 39.06v
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 34 smsc PAC1720 smsc confidential datasheet 5.11 vsource voltage registers the vsource voltage registers store the measured v source value (see section 4.4, "voltage measurement" ). the measured voltage is determined by summing the bit weights of each bit set. for example, if v source was 7.4v, the vsource voltage registers would read 0010_1111 for the high byte and 0100_0000b for the low byte corresponding to 5v + 1.25v + 0.625v + 0. 3125v + 0.1563v + 0.0390v = 7.3828v. the bit weightings are assigned for human interpreta tion. they should be disregarded when translating the information via a comp uting system as shown in section 4.4, "voltage measurement" . the vsource voltage registers cannot support negat ive values, so all values less than 0v will be recorded as 0v. table 5.19 vsource voltage registers addrr/wregisterb7b6b5b4b3b2b1b0default 11h r ch1 vsource voltage high byte 20 10 5 2.5 1.25 0.625 0.3125 0.1563 00h 12h r ch1 vsource voltage low byte 0.0781 0.0390 0.0195 - - - - - 00h 13h r ch2 vsource voltage high byte 20 10 5 2.5 1.25 0.6250 0.3125 0.1563 00h 14h r ch2 vsource voltage low byte 0.0781 0.0390 0.0195 00h
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 35 revision 1.1 (12-08-11) smsc confidential datasheet 5.12 power ratio registers the power ratio registers store a power factor value, p ratio , that is used to determine the final average power deliver ed to the system (see section 4.5, "power calculation" ). p ratio is the result of the multiplication of the v sense reading and the v source reading values shifted to a 16-bit number. it represents the ratio of delivered power with respect to maximum power. 5.13 v sense limit registers the v sense limit registers store a high and low limit for v sense . v sense is compared against both limits after each conversion cycle. the data format for the limit is a raw binary form that is relative to the maximum v sense that has been programmed. if the measured sense voltage meets or exceeds the high limit or dr ops below the low limit, the alert pin is asserted (by default - see section 4.6, "alert output" ) and the vsense_high or vsense_low status bits are set in the high limi t status or low limit status registers (see section 5.6 and section 5.7 ). application note: v sense is always checked to meet or exceed the high limit or to be less than the low limit, including when v sense is negative. table 5.20 power ratio registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 15h r ch1 power ratio high byte 32768 16384 8192 4096 2048 1024 512 256 00h 16h r ch1 power ratio low byte 128 64 32 16 8 4 2 1 00h 17h r ch2 power ratio high byte 32768 16384 8192 4096 2048 1024 512 256 00h 18h r ch2 power ratio low byte 128 64 32 16 8 4 2 1 00h table 5.21 v sense limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 19h r/w ch1 sense voltage high limit sign 1024 512 256 128 64 32 16 7fh 1ah r/w ch2 sense voltage high limit sign 1024 512 256 128 64 32 16 7fh 1bh r/w ch1 sense voltage low limit sign 1024 512 256 128 64 32 16 80h 1ch r/w ch2 sense voltage low limit sign 1024 512 256 128 64 32 16 80h
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 36 smsc PAC1720 smsc confidential datasheet 5.14 vsource voltage limit registers the vsource voltage limit registers store the high and low limits for v source . v source is compared against both limits after each conversion cycle. if v source meets or exceeds the corresponding high limit or drops below the low limit, the alert pin is asserted (by default - see section 4.6, "alert output" ) and the vsrc_high or vsrc_low status bits are set in the high limit status or low limit status registers (see section 5.6 and section 5.7 ). 5.15 product id register the product id register holds a unique value that identifies the device. 5.16 smsc id register the manufacturer id register contains an 8-bit word that identifies smsc as the manufacturer of the PAC1720. table 5.22 vsource voltage limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1dh r/w ch1 vsource high limit 20 10 5 2.5 1.25 0.625 0.3125 0.1563 ffh 1eh r/w ch2 vsource voltage high limit 20 10 5 2.5 1.25 0.625 0.3125 0.1563 ffh 1fh r/w ch1 vsource voltage low limit 20 10 5 2.5 1.25 0.625 0.3125 0.1563 00h 20h r/w ch2 vsource voltage low limit 20 10 5 2.5 1.25 0.625 0.3125 0.1563 00h table 5.23 product id register addrr/wregisterb7b6b5b4b3b2b1b0default fdh r product id 01010111 57h table 5.24 manufacturer id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fehrsmsc id01011101 5dh
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 37 revision 1.1 (12-08-11) smsc confidential datasheet 5.17 revision register the revision register contains an 8-bit word that identifies the die revision. table 5.25 revision register addrr/wregisterb7b6b5b4b3b2b1b0default ffh r revision10000001 81h
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 38 smsc PAC1720 smsc confidential datasheet chapter 6 package description 6.1 PAC1720 package drawin g (10-pin dfn) figure 6.1 10-pin dfn package drawings
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 39 revision 1.1 (12-08-11) smsc confidential datasheet figure 6.2 10-pin dfn package dimensions figure 6.3 10-pin dfn recommended pcb land pattern
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 40 smsc PAC1720 smsc confidential datasheet 6.2 PAC1720 package markings the PAC1720 is marked as shown in figure 6.4 . figure 6.4 PAC1720 package marking bottom line 1: device code (dd), first 2 of last 6 digits of lot number line 2: last 4 digits of lot number top e4 pin 1 bottom marking is not allowed 2 6 l l l l l l
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 41 revision 1.1 (12-08-11) smsc confidential datasheet chapter 7 application usage 7.1 electrical overstress a common question during system board level design is about the capability of an integrated circuit (ic) to withstand electrical over stress. this question tends to focu s on the device inputs, but may involve the supply voltage pins and even the output pins. each of these different pin functions has electrical stress limits mainly determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific internal ic circuit connected to the pin. additionally, internal electrostatic discharge (esd) protection is built into these circuits to protect them from accidental esd events before and during product a ssembly, as well as during normal operation. for the previously described reasons, it is helpf ul to have a good understanding of this basic esd circuitry and its relevance to an electrical overstress event. figure 7.1 illustrates the esd circuits contained in the PAC1720 series (indicated by the shaded box). the esd protection circuitry involves several current-steering diodes connected from the input and output pins to absorption devices internal to the ic. this protection circuitry is intended to remain inactive during normal circuit operation. an esd event produces a short duration, high-volt age, high-current pulse which discharges through the semiconductor device. the esd protection circuits are designed to provide a current path around the internal ic core while limiting the voltage to prevent the ic from being damaged. the energy absorbed by the protection circuitry is then dissipated as heat. when an esd voltage develops across two or more of the ic device pins, current flows through one or more of the steering diodes. depending on the path the current takes, the absorption device may activate. fast changing voltage on the pin generally acts as a trigger, and the absorption device will quickly clamp the voltage across the supply rails to a safe level. when the PAC1720 connects into a circuit such as the one figure 7.1 shows, the esd protection components are intended to remain inactive and not become involved in the application circuit operation. however, circumstances may arise wher e an applied voltage exceeds the operating voltage figure 7.1 equivalent internal esd circuitry sense1+ sense1- sense2+ sense2- edge-triggered esd absorption circuit PAC1720 core edge-triggered esd absorption circuit addr_sel smclk smdata alert v dd r s (2) + v in (1) + gnd notes: (1) v in =-500mv (2) r s needs to limit current to 10ma
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 42 smsc PAC1720 smsc confidential datasheet range of a given pin. should this condition occur, there is a risk that some of the internal esd protection circuits may be biased on and conduct current. figure 7.1 depicts a specific example where the input voltage, v in , is below ground by more than 500mv. the bottom steering diode will conduct and di rect current to gnd. excessively high current levels can flow with increasingly lower v in . the current limiting resistor r s is recommended, by datasheet specification, to keep the input current lower or equal to 10ma. 7.2 PAC1720 internal filtering the application circuit shown in figure 4.1, "PAC1720 system diagram" does not need any additional filters on the sense+ and sense- input pins. the PAC1720 has internal circuitry to handle noise, so external filters are not necessary, and in fact, will introduce errors. this section describes noise and the PAC1720?s methods for handling noise internally. due to high efficiency, low weight, and low volume, switch mode power supplies (smps) are used in most equipment today. accurate measurement of cu rrent and voltage can be challenging due to the inherent noise of the smps. this noise is well known and defined. sometimes external noise can be present which is much more difficult to predict. the PAC1720 offers several options for dealing with the noise. the signal will first pass through the esd structure which will protect the internal circuit from possible electrical overstress. next it passes a built-in analog filter before the internal, high- performance analog-to-digital converter (adc). this adc is based on the delta-sigma ( ? ) structure. this type of conver ter has very good inherent noise rejection due to oversampling and digi tal filtering of the sampled signal. transients that occur at or very close to the sampling rate harmonics will be rejected due to the internal analog filter. in addition, advanced rolling averaging (8x) of the signal with variable sampling time (82ms to 2.6s) will remove any remaining noise. overload conditions of the smps can be another consid eration for the system-l evel designer. one scenario might be a short to ground on the load side of the shunt. this type of event can result in increased voltage across the shunt resistor (as long as the power supply or energy storage capacitors support it). it is very unlikely th at the short circuit current will be 100 times higher than the maximum nominal current. also, in this case, the PAC1720 maximum differential voltage of 42v will prevent damage to the part. it must be remembered that removing a short to ground can result in inductive kickbacks that could exceed the absolute maximum voltage of all components connected to this line. inductive kickback voltages are best dealt with by zener-type transient-absorbing devices (commonly called transzorbs) combined with suff icient energy storage capacitance. in the case of the equipment malfunctioning and a ha rd physical short, this is most likely to cause excessive dv/dt present on the inputs of the PAC1720. some applications that do not have large energy storage electrolytic capacitors on one or both sides of the shunt can be subject to this overstress. the PAC1720 esd structure is designed to activate on the fast rising edge (an esd event has a rising edge of less than 10ns). in the normal application, some capacitance is always present. to trigger the internal esd structure of the pac1 720 when 1f capacitor is present, a step current of approximately 1.2ka needs to be applied, as shown in equation [7] . 7.3 do not apply a filter across the current shunt adding filter on the sense+ and sense- input pins will induce offset and cause accuracy error. this section explains the error that is introduced when unnecessary filters are added. as described in the section above, the PAC1720 has the internal circuitr y to provide filtering without the need for external filters. figure 7.2 shows an example of unnecessary filter resistors r filt on the input pins. [7] ic ? v ? t ----- - 1 f 12 v 10 ns ------------- 1200 a = ==
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 43 revision 1.1 (12-08-11) smsc confidential datasheet in the normal operation without the added filt ers, the voltage to measure is shown in equation [8] . to properly account for the offset error, tbd v is added to this measurement, as shown in equation [9] . the input bias current of the input circuit in combination with added filter resistor r filt (in this example 10 ) will interfere with the measurement and add error, as shown in equation [10] and equation [11] . assuming the input bias current on both pins has the same direction, total added error is shown in equation [12] and equation [13] . adding resistors on the sense+ and sense- input pins will induce error which is several times greater than the inherent maximum offset error. for that reason, we do not recommend putting any additional filter on these input pins. figure 7.2 PAC1720 with unnece ssary filters on the input pins [8] [9] [10] [11] [12] [13] adc + v bus v sense = r sense x i load i load r sense emc17x0 sense + sense - i sense- i sense+ r filt r filt sense + sense - ? v sense r sense i load = = v sense _ off _ max tbd lsb @80mv tbd 39.08 vtbd v = = = v r + r filt i sense + 10 150 a 1500 v = = = v r - r filt i sense - 10 5 a 50 v = = = v error v r + v r - ? 1500 v 50 v 1450 v = ? = = v error 1450 v 39.08 v ---------------------- - 37 lsb @80mv = =
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 44 smsc PAC1720 smsc confidential datasheet 7.4 initial device configuration after power-up, configure the PAC1720 as follows: 1. disable all channels by setting conf iguration register 00h to 1bh (see section 5.2, "configuration register" ). 2. wait up to 220ms; read back configurati on register 00h to ensure it?s set to 1bh. 3. set conversion rate in conversion rate register 01h (see section 5.3, "conversion rate register" ). 4. enable desired channel enables in configuration register 00h.
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 45 revision 1.1 (12-08-11) smsc confidential datasheet chapter 8 typical operating curves figure 8.1 idd vs vdd f igure 8.2 idd vs vdd figure 8.3 idd vs vdd figure 8.4 isense+ pin current vs vbus figure 8.5 isense+ pin bias current figure 8.6 isense- pin bias current continuous conversions 460 480 500 520 540 560 580 600 3.0 3.3 3.6 4.5 5.0 5.5 vdd [v] idd [ua] ta=25c ta=-40c ta=85c 1 conversion per second, low est resolution 10 12 14 16 18 20 22 3.0 3.3 3.6 4.5 5.0 5.5 vdd [v] idd [ua] ta=25c ta=-40c ta=85c standby mode 3 4 5 6 7 8 9 10 11 12 13 3.0 3.3 3.6 4.5 5.0 5.5 vdd [v] idd [ua] ta=25c ta=-40c ta=85c ta = -40c to 85c \ 20 0 20 40 60 80 100 120 0 1020304050 vbus [v] isense+ current [ua] 80mv range 97.5 98.0 98.5 99.0 99.5 100.0 100.5 101.0 101.5 102.0 \ 100% \ 7 5% \ 50% \ 2 5% 0% 25 % 50 % 75 % 1 0 0% vsense [% of full scale] isense+ current [ua] ta=25c ta=85c ta=-40c 80mv range, ta=-40c to 85c \ 0.20 \ 0.15 \ 0.10 \ 0.05 0.00 0.05 0.10 0.15 0.20 \ 100% \ 75% \ 50% \ 25% 0% 2 5 % 5 0% 7 5% 10 0% vsense [% of full scale] isense- current [ua]
dual high-side current sense m onitor with power calculation datasheet revision 1.1 (12-08-11) 46 smsc PAC1720 smsc confidential datasheet figure 8.7 isense+ pin leakage current fi gure 8.8 isense- pin leakage current figure 8.9 isense+ pi n current vs vbus ta = -40c to 85c \ 0.020 \ 0.015 \ 0.010 \ 0.005 0.000 0.005 0.010 \ 1 00% \ 8 0% \ 6 0% \ 4 0% \ 2 0% 0% 20% 40 % 60% 80% 10 0% vsense [% of full scale] isense+ current [ua] ta = -40c to 85c \ 0.020 \ 0.015 \ 0.010 \ 0.005 0.000 0.005 0.010 \ 100% \ 80% \ 6 0% \ 40% \ 20% 0% 20% 40% 60% 80% 1 0 0% vsense [% of full scale] isense+ current [ua] ta = -40c to 85c \ 20 0 20 40 60 80 100 120 0 1020304050 vbus [v] isense+ current [ua]
dual high-side current sense m onitor with power calculation datasheet smsc PAC1720 47 revision 1.1 (12-08-11) smsc confidential datasheet chapter 9 datasheet revision history table 9.1 PAC1720 customer revision history revision level & date secti on/figure/entr y correction rev. 1.1 (12-08-11) general description adde d: ?the PAC1720 device is good for measuring dynamic power. the long integration time allows for extendin g system polling cycles without losing any power consumption information. in addition the alert ensures that transient events are captured between the polling cycles.? table 2.2, "electrical specifications" changed i dd_stby from 5a typ to 5.5a. i sense+ _leak and i sense-_leak changed from 0.1 a typ to 0.01. added total power ratio measurement error () (negative range) of 2% fs r max and clarified that 1% fsr max is for positive range. table 2.3, "smbus electrical specifications" two rows added for t hd:dat . also added: bus free time stop to start, start setup time, start hold time, stop setup time, data setup time, clock low period, clock high period. section 3.1.6, "smbus and i2c compliance" added: PAC1720 supports i 2 c fast mode at 400khz. this covers the smbus max time of 100khz. added: i 2 c devices support block read and block write differently. i 2 c protocol allows for unlimited number of bytes to be sent in either direction. the smbus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. the PAC1720 supports i 2 c formatting only. section 3.3, "i2c protocols" added. moved descriptions of block write and block read to this section. chapter 8, typical operating curves added. rev. 1.0 (10-18-11) formal release

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